1. Field of the Invention
The present invention relates to an ESD circuit and, more particularly, to a 5V tolerant corner clamp with a keep off circuit and a fully distributed slave ESD clamps formed under the bond pads.
2. Description of the Related Art
An electrostatic discharge (ESD) protection circuit is a circuit that protects the input/output transistors of a semiconductor chip from an ESD event. An ESD event typically occurs when the chip is exposed to static electricity, such as when the pins or solder bumps of the chip are touched by an ungrounded person handling the chip, or when the chip slides across another surface on its pins or solder bumps.
For example, an ungrounded person handling a semiconductor chip can place a static electric charge as high as 2000V on the chip. This voltage is more than sufficient to destructively break down the gate oxide of the input/output transistors of the chip.
FIG. 1 shows a schematic diagram that illustrates a prior-art ESD protection circuit 100. As shown in FIG. 1, circuit 100 includes an ESD plus ring 110 and an ESD minus ring 112 that are formed around the periphery of a semiconductor die 114. In addition, circuit 100 includes a power pad 120, a ground pad 122, and a number of input/output (I/O) pads 124.
As further shown in FIG. 1, circuit 100 includes a plurality of upper diodes D1 that are connected to ESD plus ring 110 and the pads 120, 122, and 124 so that each pad is connected to ESD plus ring 110 via a diode D1. In addition, a plurality of lower diodes D2 are connected to ESD minus ring 112 and the pads 120, 122, and 124 so that each pad is connected to ESD minus ring 112 via a diode D2. Circuit 100 also includes four corner clamps 130 that are connected to ESD plus ring 110 and ESD minus ring 112.
In operation, when an ESD event occurs, a first pad, such as pad A, is zapped positively with respect to a second pad, such as pad B. In this situation, a zap current IZAP flows from the first pad through the adjacent diode D1 to ESD plus ring 110, and then on to corner clamps 130.
Corner clamps 130 are voltage controlled switches that each provide a low impedance pathway from ESD positive ring 110 to ESD negative ring 112 when an ESD event is present, and a high impedance pathway between rings 110 and 112 when an ESD event is not present.
When the first pad is zapped, the corner clamps 130 (which are shown open, not closed, in FIG. 1) close and the zap current IZAP flows through clamps 130 to ESD minus ring 112. From ring 112, the zap current IZAP flows through a diode D2 and on to the second pad.
FIG. 2 shows a schematic diagram that illustrates corner clamp 130. As shown in FIG. 2, clamp 130 includes a RC timing circuit 210, an inverter 212, and a switching transistor M1. Timing circuit 210, in turn, includes a resistor R that is connected to ESD plus ring 110, and a capacitor C that is connected to resistor R and ESD minus ring 112.
Inverter 212 includes a PMOS transistor M2 and a NMOS transistor M3. Transistor M2 has a source connected to ESD plus ring 110, a gate connected to resistor R and capacitor C, and a drain. Transistor M3 has a source connected to ESD minus ring 112, a gate connected to resistor R and capacitor C, and a drain connected to the drain of transistor M2. Further, switching transistor M1 has a source connected to ESD minus ring 112, a gate connected to the drains of transistors M2 and M3, and a drain connected to ESD plus ring 110.
In operation, when an ESD event occurs and the zap current IZAP flows onto ESD plus ring 110, the voltage on ESD plus ring 110 spikes up dramatically. The voltage on the gates of transistors M2 and M3 also spikes up but, due to the presence of RC timing circuit 110, the gate voltage lags the voltage on ESD plus ring 110.
As a result, the gate-to-source voltage of transistor M2 falls below the threshold voltage of transistor M2, thereby turning on transistor M2 for as long as the gate voltage lags the voltage on ring 110. When transistor M2 turns on, transistor M2 pulls up the voltage on the gate of transistor M1, thereby turning on transistor M1. When transistor M1 is turned on, clamp 130 provides a low impedance pathway from ESD plus ring 110 to ESD minus ring 112.
Once the packaged integrated circuit has been attached to a circuit board, power has been applied to the integrated circuit, and a steady state condition has been reached, a first voltage is present on both ESD plus ring 110 and the gates of transistors M2 and M3. For example, when pad 120 is a 3.3V power pad, a first voltage of 2.6V is present on ESD plus ring 110 due to the diode drop of adjacent diode D1. In addition, a second voltage is present on ESD minus ring 112. For example, since pad 122 is ground, a second voltage of 0.7V is present on ESD minus ring 112 due to the diode drop of adjacent diode D2.
Since the first voltage is present on the gates of transistors M2 and M3, transistor M2 is turned off and transistor M3 is turned on. When turned on, transistor M3 pulls down the voltage on the gate of transistor M1, thereby turning off transistor M1. When transistor M1 is turned off, clamp 130 provides a high impedance pathway from ESD plus ring 110 to ESD minus ring 112.
One problem with clamp 130 is that clamp 130 falsely triggers when used with a 5V tolerant circuit. A 5V tolerant circuit is a circuit that internally utilizes a voltage less than 5V, such as 3.3V, but receives 5V signals. For example, I/O pad C in FIG. 1 can be driven by an external driver that outputs signals ranging from zero to 5V.
When 5V signals are driven onto a signal pad, such as pad C, the voltage on ESD plus ring 110 spikes up from 2.6V to 4.3V (a diode drop less than 5V). In addition, when a large number of pads are driven to 5V at the same time, such as when the 64 pads of a PCI bus are simultaneously driven high, the voltage on ESD plus ring 110 can spike up to 4.8V.
Due to the timing lag provided by RC timing circuit 210, the spike in voltage, a delta of 1.7V to 2.2V, causes the gate-to-source voltage of transistor M2 to again fall below the threshold voltage, thereby turning on transistor M2. When transistor M2 turns on, transistor M2 pulls up the voltage on the gate of transistor M1, thereby turning on transistor M1.
Since transistor M1 turned on in response to a 5V signal rather than in response to an ESD event, clamp 130 was falsely triggered. Falsely triggering clamp 130 increases power dissipation and significantly loads the external device that is driving the signal pad.
The ESD protection circuitry used on a semiconductor chip is commonly considered to be part of the I/O cell structure of the chip. Typically, each I/O cell includes a pad, such as power pad 120, ground pad 122, or an I/O pad 124, a section of an ESD plus ring, such as ring 110, and a section of an ESD minus ring, such as ring 112.
In addition, each I/O cell includes an upper diode, such as diode D1, that is connected between the pad and the ESD plus ring, and a lower diode, such as diode D2, that is connected between the pad and the ESD minus ring. Further, each I/O cell includes a section of a clean power ring, and a section of a clean ground ring. The clean power ring, which is supplied by a first power pad, and the clean ground ring, which is connected to a first ground pad, support the core circuitry of the semiconductor chip with substantially noise free power and ground connections.
Each I/O cell also includes a section of a dirty power ring, and a section of a dirty ground ring. The dirty power ring, which is supplied by a second power pad, and the dirty ground ring, which is connected to a second ground pad, support the noisy I/O circuits. In addition, each I/O cell typically includes I/O circuitry.
FIGS. 3A-3F show a series of plan views that illustrate an example of the physical layout of a prior art I/O cell 300. As shown in FIG. 3A, I/O cell 300, which is formed in a layer of semiconductor material 302, includes a diode 304, such as diode D1 of FIG. 1, that is formed in material 302. In addition, I/O cell 300 includes a diode 306, such as diode D2 of FIG. 1, that is formed in material 302.
Further, I/O cell 300 includes I/O circuitry 312 that is formed in semiconductor material 302. I/O circuitry 312 can include, for example, MOS and/or bipolar transistors. Cell 300 also includes a number of contacts 314 that are formed through a first layer of dielectric material to make an electrical connection with diodes 304 and 306 and I/O circuitry 312.
Referring to FIG. 3B, I/O cell 300 additionally includes a first pad P1 and a number of first regions 316 that are formed from a first layer of metal. Pad P1 and the first regions 316, which include first regions 316A and 316B, are formed so that pad P1 and the first regions 316 make electrical connections with contacts 314. Cell 300 also includes a number of vias 320 that are formed through a second layer of dielectric material to make electrical connections with pad P1 and the first regions 316.
Referring to FIG. 3C, I/O cell 300 additionally includes a second pad P2 and a number of second regions 322 that are formed from a second layer of metal. Pad P2 and the second regions 322, which include second regions 322-A, 322-B, and 322-C, are formed so that pad P2 and the second regions 322 make electrical connections with vias 320.
Cell 300 also includes a trace 324 that is formed from the second layer of metal. Trace 324 is connected to pad P2, second region 322-A, and second region 322-C. Cell 300 also includes a number of vias 330 that are formed through a third layer of dielectric material to make electrical connections with pad P2 and the second regions 322.
Referring to FIG. 3D, I/O cell 300 further includes a third pad P3, a section of a first ESD plus ring 340, and a section of a first ESD minus ring 342. In addition, I/O cell 300 includes a section of clean power line 344, and a section of a clean ground line 346. Further, I/O cell 300 includes a section of a dirty power line 350, and a section of a dirty ground line 352. Pad P3, rings 340 and 342, and lines 344, 346, 350, and 352 are formed from a third layer of metal.
Pad P3, rings 340 and 342, and lines 344, 346, 350, and 352 are also formed to make electrical connections with vias 330. Cell 300 additionally includes a number of vias 354 that are formed through a fourth layer of dielectric material to make electrical connections with pad P3, rings 340 and 342, and lines 344, 346, 350, and 352.
Referring to FIG. 3E, I/O cell 300 additionally includes a fourth pad P4, a second ESD plus ring 360, and a second ESD minus ring 362. In addition, I/O cell 300 includes a clean power line 364, a clean ground line 366, a dirty power line 370, and a dirty ground line 372. Pad P4, =rings 360 and 362, and lines 364, 366, 370, and 372 are formed from a fourth layer of metal.
Pad P4, rings 360 and 362, and lines 364, 366, 370, and 372 are also formed to make electrical connections with vias 354. Cell 300 also includes a number of vias 374 that are formed through a fifth layer of dielectric material to make electrical connections with pad P4, rings 360 and 362, and lines 364, 366, 370, and 372.
Referring to FIG. 3F, I/O cell 300 further includes a fifth pad P5, a third ESD plus ring 380, and a third ESD minus ring 382. In addition, I/O cell 300 includes a clean power line 384, a clean ground line 386, a dirty power line 390, and a dirty ground line 392. Pad P5, rings 380 and 382, and lines 384, 386, 390, and 392 are formed from a fifth layer of metal. Pad P5, rings 380 and 382, and lines 384, 386, 390, and 392 are also formed to make electrical connections with vias 374.
Together, pads P1-P5 form a bonding pad, such as pad 120 of FIG. 1. Together, ESD plus rings 340, 360, and 380 form an ESD plus ring, such as ring 110. Together, ESD minus rings 342, 362, and 382 form an ESD minus ring, such as ring 112.
As further shown in FIG. 3F, I/O cell 300 has an I/O cell height X that is measured laterally from the edge of the die and includes the widths of pad P5, rings 380 and 382, and lines 384, 386, 390, and 392. Pad P5, the pair of rings 380 and 382, the pair of lines 384 and 386, and the pair of lines 390 and 392 each require about the same amount of silicon real estate.
In operation, when an ESD event occurs on pad P5, the voltage spike passes through vias 374 to pad P4, and from pad P4 through vias 354 to pad P3. The voltage spike continues through vias 330 to pad P2, and from pad P2 through trace 324 to region 322A. The spike continues through vias 320 to region 316A, and from region 316A through contact 314 to diode D1.
The voltage spike passes through diode D1, through contact 314 to region 316-B, and from region 316-B to via 320, and then to region 322-B. From region 322-B, the spike continues to via 330, and then to ESD plus ring 340. From ESD plus ring 340, the spike moves to ESD plus rings 360 and 380 by vias 354 and 374.
Although ESD protection circuit 100 functions satisfactorily, there is a need for alternate ESD protection circuits and layouts.
The present invention provides an ESD protection circuit that includes a number of 5V tolerant ESD master and slave clamps that do not falsely trigger when a 5V signal is driven onto a signal pad. The ESD circuit, which is formed on a semiconductor die, has an ESD plus ring and an ESD minus ring that are formed on the die around the periphery of the die.
The ESD circuit also has first and second trigger rings that are formed on the die around the periphery of the die, and a plurality of first clamps formed on the die. Each first clamp has-first and second diodes that are formed on the die. The first diode is connected to a pad and the ESD plus ring. The second diode is connected to the pad and the ESD minus ring.
The ESD circuit further has a first transistor that is connected to the ESD plus ring, the first trigger ring, and a first node, and a second transistor that is connected to the first node, the second trigger ring, and a second node. In addition, a third transistor is connected to the ESD minus ring, the second trigger ring, and the second node, a fourth transistor is connected to the ESD plus ring, the first node, and a third node, and a fifth transistor is connected to the second node, the third node, and the ESD minus ring.